1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, to a semiconductor device manufacturing method using an imprinter.
2. Related Art
In recent years, as one of resist pattern transferring methods has been known as an optical nano-imprinting. The optical nano-imprinting includes filling a space defined between a template having a shape of a resist pattern and a substrate to be transferred with an imprinted resin of a monomer; irradiating the template and the substrate to be transferred in contact or proximity with each other with light; and crosslinking the imprinted resin so as to transfer the resist pattern. It is unnecessary to interpose an optical projecting lens between the template and the substrate in the optical nano-imprinting, with an advantage that the pattern shape of the template can be transferred to the imprinted resin on the substrate in a one-to-one size.
In contrast, in manufacturing a semiconductor device, a stereoscopic circuit pattern is made by repeating optical nano-imprinting a plurality of times and processing a substrate to be transferred. Therefore, it is necessary to perform operation (hereinafter referred to as “alignment”) for controlling the position, size, and shape of a resist pattern to be transferred by using the optical nano-imprinting in manufacturing the semiconductor device according to the position, size, and shape of a pattern formed already on a lower layer of the substrate to be transferred (hereinafter referred to as “a primary pattern”), and thus, forming the resist pattern in conformity with the primary pattern. In the alignment, differences in size and shape between the primary pattern and the template cause the degradation of the performance of the semiconductor device.
In the alignment for the optical nano-imprinting in the prior art, the template is deformed by applying force to the periphery thereof, thereby allowing the size and shape of a pattern formed on the template to conform to those of the primary pattern (see U.S. Pat. No. 6,916,585). At this time, there is manufactured a template which is enlarged under a magnification correctable by an imprinter with respect to the primary pattern. Therefore, in order to manufacture the template enlarged under such a magnification, the conventional alignment needs design data enlarged under the same magnification.
However, the magnification correctable by the imprinter is as very small a value as about several ppm to the maximum. Therefore, variations in position and size of the pattern in the design data enlarged under the magnification are smaller than a grid size of the design data made by a CAD or the like. Therefore, it is possible that the size of the pattern may be varied when the position of the pattern falls in positional coordinates which are large to some extent. As a result, a rounding error occurs in the size or position of the pattern.
An adverse influence of such a rounding error can be reduced by more reducing the grid size of the design data. However, a pattern writer for manufacturing a template cannot cope with a small addressing size enough to reduce the adverse influence of such a rounding error. In the same manner, a rounding error occurs also when the pattern writer writes or produces data for writing. Therefore, the resist pattern formed by the optical nano-imprinting using such a template undesirably includes large alignment error in imprinting. The larger the alignment error becomes, the lower the yield of the semiconductor device gets.